The aim of the project was to design, build, test and report back on a microprocessor based solution for a non fade time compressed memory display for physiological data, in particular the electro-cardiograph(ECG). The microprocessor chosen was the Motorola 68008, which, using a software program written in 68000 assembly language, controlled the acquirement of ECG data samples, the storing of these samples and the output of them at a much higher frequency than that at which they were sampled. A switch was also included which would freeze the display if required.

Acknowledgments

I’d like to thank the staff of block 6 for their help and patience throughout this project, namely Paul Comaskey and Billy Byrd, thankyou for your support over the last few months. I would also like to thank Mr Andrew Brown for his help and support at a time when he was also coping with a busy workload.

Introduction

In order to obtain a good quality image from an electro-cardiograph (ECG) it is necessary to use the system of time compression. This is were we output the sampled data at a much faster rate from that which it is obtained. The reason this is necessary is to avoid the "bouncing ball" effect which would be obtained with a slow display rate, this would make the display extremely difficult to read and hence not very user friendly.

Time Compression is achieved via outputting the data obtained from the ECG at a rate that is faster than the flicker threshold of the eye ie 50Hz, and thus the trace obtained appears to be permanent/solid. In order to output the data at this rate the sampled data must be temporarily stored in RAM and read from many times faster than it is updated. The display is then of the nonreal time type.

• General To implement a microprocessor design solution for a non-fade (time-compressed) memory to display physiological data.
• Display Non fade with hold facility.
• Screen Width 50mm
• Moving Trace Speed 25mm/sec
• Bandwidth 0.05 - 20Hz
• Input Requirement 1mV (differential) with at least 70dB CMRR
• Output Requirement X Data,Y Data,Z Modulation
• Power Supply External sources may be used
• Display Medium Standard Oscilloscope
• Microprocessor Motorola 68008

Digital Hardware Design

Z Modulation

I decided to replace the Z modulation by using a bi-directional timebase that would sweep in one direction and then the other. This has many advantages, firstly it eliminates the need for a Z modulation latch and thus reduces the chip count. Also to provide fly back blank on a standard oscilloscope would require approx. 30 Volts. Generation of this voltage would require additional power supplies and a relay circuit, and hence increase the amount of circuitry required. Therefore a bi-directional solution seems the better option.

Sampling and Freeze

The idea here was to use a hardware solution, via interrupts, to force the microprocessor to take a sample from the A/D. Hence a simple switch could be inserted to stop the interrupts, when no interrupts where received the screen would effectively freeze as it continually took the non-changing values from RAM. The hardware approach has many advantages over a software approach to interrupts. The main advantage is that the sampling frequency can be easily adjusted by a hardware solution via a POT. The circuitry involved is based around a 555 timer and described fully in later sections. A software solution would require the use of NOP commands to pad the outputting procedure until the desired sampling interval was filled which would require precise timing details. I decided to predict if the solution would work with my proposed circuit solution. From the specification:- Screen width = 50mm Moving trace speed = 25mm/sec Bandwidth = 0.05 - 20Hz ( in two seconds, that being the time taken for the image to cross the screen) 256 samples need to be stored. Deciding to take one sample per sweep would mean the sampling frequency would be 2/256 = 7.8125 msecs. Hence for a screen refresh rate of 128Hz, the time to display each data point is 7.8125/256 = 30.5usecs. This was considered more than enough time to output a single data point to the display, so the design continued. Circuit Description

1.1 Microprocessor

The Motorola 68008 microprocessor was chosen for the project development, the reason being that this was the processor that I had studied in the second year of my course and thus I was familiar with it. It could be argued that this processor is too powerful for this application but the relative price differences between the 68000 chip and the 6800 is negligible and hence is not of concern. All the pins on the chip were used with the exception of Address lines A16 to A19 which were not required and also BG and E whose use was also not required. BERR and BR were both tied high.

1.2 Address Decoding

The memory map for the system and the associated decoding is shown below:

A15 A14 A13 A0

Address

Initially the idea was to use a PAL 20L8 for decoding purposes as this would have given me valuable experience in the use of PAL programming and programmers however due to the size of the project and the time constraints I settled with using a 3 to 8 line (138) decoder as this was a proven and ultimately easier method.

1.3 Reset Circuitry

It was decided to use a 555 timer for the reset circuitry, the circuitry shown later is a common method for resetting the processor as it also deals with the problem of ‘cold starts’.

1.4 Header

A 20 pin header was used to enable the 68008 to be placed in free-run mode by shorting the data bus to ground and floating DTACK high. This means the correct operation of the processor could be established by monitoring the address lines which should now act as a 20 bit counter.

1.5 EPROM

A 27NMC64 EPROM was used in the circuit. This provided 8 Kilobytes of memory in which to store the program, which was more than enough for our purposes. The SPRINT software was used to program the EPROM, the programs can be found later in the book. The programs were assembled using a 68008 assembler, which produced a Hex file. This file was then loaded into the SPRINT package and was used to program the EPROM. The EPROM was selected by driving the OE pin low. The CE pin of the EPROM was also connected, through and invertor, the R/W pin of the processor as a safety measure to ensure the EPROM is never written to.

1.6 Interrupt Generator.

The 68008 needs to receive an interrupt before it will jump to a subroutine to take in a new sample from the A/D. A 555 timer was used to generate a negative going pulse which would drive the interrupt pin IPL0/2 and IPL1 low and force the 68008 to respond to the level 7, non-maskable interrupt. The 555 timer is used in astable multivibrator configuration. The frequency of the output waveform can be determined from the expression F = 1/(R1+R2)*2

R1 was made a 200K pot to enable a relatively large variance in possible sampling frequencies. When a negative pulse is received on the 68008 interrupt pins, the microprocessor drives the function pins FC0,FC1 AND FC2 high to indicate that it has received an interrupt. Using the autovector circuitry, as can be seen in the circuit diagram, VPA is now driven high, the processor now looks up the vector table to find the level 7 interrupt routine address, vector 31. Thus the 68008 jumps to the subroutine which takes in a sample from the A/D and returns from the interrupt. A software interrupt solution was first considered which would obviously be more accurate however the ease of adjustability of the hardware solution won the day. Allowing easier variance of the sampling frequency.

1.7 Freeze

The freeze switch simply prohibits the microprocessor from receiving any interrupts. Hence it does not take any samples from the A/D converter and simply outputs the contents of RAM which gives the appearance that the trace is frozen.

1.8 RAM

An 8 kilobyte, the 6264, RAM chip was used to store the data samples. Again this chip has more than enough room for our purposes. The chip was enabled by driving the CS1 pin low from the decoder and also by driving the CS2 pin high from the DS of the microprocessor.

1.9. Analogue To Digital Converter

The Analogue to Digital converter chosen for the project was the ZN439. It has a 5(S conversion time which was more than adequate for the time compressed memory display system. The A/D was setup for bipolar operation (ie the incoming signal being bipolar). This only meant the addition of a few extra discrete components and meant that the ECG would have to be level shifted above 0 volts. Vref was set to 2.5 Volts thus the input range was + 2.5 Volts (5 Volts peak). The A/D was put in a mode for continuos conversion of the incoming data but the output latch would only be enabled by the 3x8 decoder driving the RD pin low. The on chip clock was set at 1Mhz by an external resistor and capacitor.

1.10 Digital To Analogue Converter

A dual Digital to Analogue convertor was chosen in the shape of the ZN508. The decision to chose DAC A or DAC B was given by Address line A0 being connected to pin 6. With pin six driven low DAC A was selected and when driven high DAC B was selected. The addresses, as can be seen in the memory map, were 2000h and 2001h. The D/A itself was selected via the decoder driving the enable pin low. It was also setup for unipolar output operation. Two 741 opamps were used to amplify the output voltage to 0-5 Volts.

Implementation of the Digital Circuit

The time compressed memory system was constructed on a 22cm x 10 cm Eurocard. All IC’s were placed in chip holders to aid easy removal, the board was wire wrapped with a general colour code to aid wire tracing.

Data Bus = Blue

Address Bus = White

Control Bus = Orange

Clock = Purple

Freeze/Interrupt Circuitry = Yellow

Decoupling Capacitors were placed between Vcc and Ground on all I.C.s to reduce noise. On completion of the board wiring each wire was individual tested to insure its correct location and to ensure there were not short circuits or bad connections. Initially it was decided to leave the analogue circuitry as a separate component on a second smaller board. If time permitted then the analogue/filtering circuitry would be constructed and connected to the main body of the ECG system

Analogue Hardware Design

2.1 Analogue Hardware Requirements

Additional analogue hardware was required in order to produce a signal which would be suitable for input to the A/D of the time compressed circuit. A separate smaller board was constructed for this circuitry simply so that the two sections could be easily viewed, obviously in a real world application they would all be one unit.

2.1.1 Instrumentation Amplifier and Highpass Filter

The highest Amplitude of an ECG signal is 1mV peak to peak, therefore we would require a gain of approx. 5000 in order to get a signal which would be suitable for our A/D input. The instrumentation amplifier constructed also includes a highpass filter to filter out frequencies below 0.05 Hz and hence produce an output in the range as required by the specification.

2.1.2 Lowpass Filter

The lowpass filter is necessary to restrict the frequency content of the ECG signal to 20Hz so in effect we have constructed a bandpass filter. The lowpass filter used was the VCVS chebychev with a gain of 10. Testing and Results

2.1 Microprocessor

The free running header was established to ensure correct operation of the processor. As described previously this shorted the data bus and made the processor into a 20 bits counter, this was observed via using a logic probe on the address pins of the processor. Proper operation of the processor was observed. The plots of Address lines A0 and A1 can be seen over leaf, this pattern of halving the frequency was observed all the way along the address bus, these plots were included as to demonstrate the theory.

Results from free running header test.

Output at A0.

Output at A1.

Output at A2.

2.2 Reset Circuitry

The rest circuitry was now tested. The circuit was observed to reset the processor both on power up and on depression of the reset switch. This observation was made with a logic probe set on the halt and reset pins, it was unnecessary to include a plot to demonstrate this fact.

2.3 Interrupt Circuitry

As described earlier the interrupt circuitry consisted of a 555 timer of some other external circuitry. With the use of an oscilloscope the interrupt pins on the processor were examined to see if they were being driven low by the interrupt circuitry. Also by adjusting the 200k potentiometer it was easy to see that the frequency of the interrupts varied in relation to the resistance. At this stage the freeze switch was also tested, correct operation was observed by the fact that changing the pot made no difference and the screen appeared to be frozen, also the interrupt pins were observed to have been tied high.

2.4 Digital to Analogue Converter Test

The D/A was tested using a simple software program which was carried over from my second year studies. The program simply outputs a bi-directional ramp to both output ports of the dual D/A. Having had my initial suspicions I soon realised that the data lines given on the data sheet for the D/A were wrong in that they were shown back to front ie the MSB being D7 and the LSB being D0. However D0 was actually the MSB and vice versa for D7. The circuit was rewired and I carried on with the software test. The test routine is shown overleaf and the bi-directional ramps are on the following page. Correct operation was confirmed by the results obtained.

Results from D/A Test

D/A Output 1

2.5 RAM Test

Every location in RAM was tested using the simple program overleaf. The idea of the program was to write out 10101010 to each byte location and then read it back and test for errors. After this 01010101 was written to each byte location in memory and read back to test for errors. If an error was detected the routine sent the value 7f hex to both channels of the D/A which resulted in an output of 1.25 Volts.

2.6 Analogue to Digital Test

Again this is a simple routine which tests the A/D convertor. The routine takes a sample from the A/D, connected to a sine wave generator, and then sends the sample back out through the D/A. It then waits for the A/D to finish converting the next sample and repeats the process as before. The program can be seen overleaf.

The results from this experiment were impressive as can be seen from the resulting graphs. The first graph was obtained by observing the input directly at the An_Input of the A/D (pin 7) and the output at Va_Out of the D/A (pin 2). As can be seen the output was a slightly lesser amplitude than the input. This was to be expected as the Vref’s on both chips are unlikely to be exactly the same and hence a difference could be expected. The second graph is taken from the actually ECG input and from the X-Out port and hence used the op-amps, confirming their operation. As can be easily seen with manipulation of the variable resistors I was able to obtain the exact value at the output of the D/A as was inserted at the input of the A/D.

Results from A/D Test.

A/D Result (i)

A/D Result (ii)

2.7 Integrated System Tests

(a) Variance of Sampling Frequency

We were now to test the ability to vary the sampling frequency using the pot, as previously described. For this the main program, which at this stage had already been written, was used. A 20Hz offset sine wave input was generated and the sampling frequency was set at 128 Hz, six time that of the input frequency. Hence we were sampling at a rate of six samples per cycle. The idea was to generate an output wave form for this sampling rate and then compare this to another waveform with the sampling rate at approx. 25 times the input frequency this would have generated two quite different waveforms which were to be plotted. Unfortunately the digital Oscilloscope was unable to print the outputs generated by the system test. This problem occurred as for the first time we used the X-Y inputs of the oscilloscope, ie one lead connected to drive the X input and the other the Y. In the previous tests we had used the leads in the normally way with their own time base. The CRO was unable to capture the time compressed and hence the following page contains a sketch of what was observed. Dr.Katzen was able to confirm that the system produced this output. It should also be pointed out that to obtain this sketch the halt switch was applied which confirmed that it functioned correctly. An observation that can not be made from the sketch is that the output was slightly offset each time a screen sweep occurred. This produced a display which, as it sweeped, cleared the offset sweep from the previous set of samples and hence did not produce a plot which appeared to be a continuos movement. The reason for this was that the CRO was not designed to the give the precession required by my software. This was the major flaw in the design. Upon initial design it would have been impossible to predict that such an error would occur, the only answer to which is a better CRO or to resort to the traditional method of Z-Modulation and fly back blank which had been used in previous years. At this stage development stopped, it's fair to say that with the use of an arrhytmia simulator input we would have gained a recognisable ECG 'human heartbeat' output. However, due to the nature of the error produced by the CRO offset the output would have appeared to be overwriting itself . The system itself has proved to be fully functional and the hardware designed is 100% correct, however with a new software design to incorporate the Z-Modulation requirement, new hardware would also be required. It was decided that this was not viable in the time required and as the project could be seen to function to specification development was stopped at this stage.

Main Program

The time compressed hardware can be seen to function properly from the output of the main program and hence it is fair to say the project was completed to a satisfactory degree. It may have been an error in judgment to initially decide to use a side to side sweep method over the more usual Z-Modulation/Screen blanking method. The problems with the sweep method have already been described, ie the inability of the CRO to give a precision output results in a dual-type display output, were the right-to-left output is slightly offset from to left-to-right output producing a visible write-over sweep. Further development of the system with a view to using the more traditional Z-Modulation method would produce a better working model with a better display ability. For this, an alternative software solution would be required. Over-all the project can be seen as a success as a time-compressed system was designed, built and tested producing visible and accountable results. The solution produced was by no means the optimum solution but with more time and more testing it would be satisfactory to say that a fuller more acceptable model could be produced using the knowledge gained from the assignment. The mini-project was very challenging and brought together all of what was learnt in all four years of the course. Speaking for myself it was personally a challenge as this is the first time I've actually had the chance to built a project of any great size or purpose so that in itself was testing. I have learnt many things during the past few months, not only wiring wrapping skills and circuit lay out considerations but also the ability to build a circuit in a modular approach. In this way every element of the circuit can be individually tested and therefore the circuit is built on a sound engineering principle ie each section is confirmed as working so more time is saved when it comes to debugging. So, in all, this had provided me with a great challenge and learning experience, from the initial specification when there seemed like a mountain to climb, through the circuit design with the available CAD packages, through construction and testing and eventually resulting in a final product. The result produced was not perfect but it did achieve the initial aim which was to build a time compressed memory system and so it can be viewed as a success Working alone on the project I opted to give only a proposal for how the analogue filter section would work, a diagram of which can be found in the Appendix. The theory of how it would work is explained in the appropriate sections in the write up. It was decided to concentrate on the main part of the system instead, as which the time considerations it was deemed better to get the largest part of the project working. The analogue circuitry would have been tested using PSpice software and then added to the circuit on completion to effectively filter the incoming signals.

Recommendations

If this system were eventually to be used in the medical field the incorporation of an opto-isolator at the front end of the circuitry would be vital to insure against electric shock. Another addition would also be internal power supplies to increase the user friendly nature of the product.

The final circuit

ECG Design and Recommendations

The ECG market is not a new one, ever since Italian physicist Carlo Matteucci discovered that an electric current accompanies each heart beat, back in 1842, many people have seized upon the idea of using the current generated by the heart for medical purposes. As early as 1887, the British physiologist Augustus D. Waller of St Mary's Medical School, London, published the first human electrocardiogram. It was recorded from Thomas Goswell, a technician in the laboratory. The first system was commercial system was purchased in 1908Edward Schafer of the University of Edinburgh. He purchased the string galvanometer (early form of ECG) for clinical use at the university. So the ECG is not a fairly new technology, indeed it has been around for almost 100 years. Since the ECG has been around for such a number of years it is no surprise that significant developments have been made and the market is filled with various different machines all with the latest technological advances. For this reason it would be fair to say that our system, whilst appropriate to do the job would not be a financially viable product for the modern market place. As an example of some of the modern ECG's available I have included some of the newest machines discovered during market research.

This is an example of a transport/portable monitor that can provide: Alarm Recalls, ST Segment Analysis Two Invasive Pressures, Telemetry and Touch screen technology. Has a battery life of 3 hrs and weighs only 4 lbs!! The DS-5100E costs approx. $10,000.00

This is another member of the DS5000 series. This system provides inputs for 8 ECG signals making the machine more cost effective and ultimately more efficient.

The PC-ECG system is the most cost effective system available as it allows you to simply connect the system up to a PC and using special software your PC effectively does all the computations that the above systems do except you don't have to buy all the expensive hardware and display mechanisms. The PC-ECG system is a versatile, full featured 12-lead ECG The system comes in different configurations to fit your needs and requirements. From a low-cost version to simply capture the heart signals to a full blown monitoring system with stress testing program, rhythm analysis and the most comprehensive measurement functions. Use the optional, unique Interface-Multiplexer to connect a blood pressure instrument, treadmill and spirometer to just one serial port at your PC.

Easy upgrade option from PC-ECG to PC-ECG pro and PC-ECG plus!

Most modern displays look like this one with various options available to the user. Numerical values are given for the heartbeat as well as other cardiac information which may prove useful to doctors. A help menu is even provided for first time users and an option to display all 8 ECG inputs or to exam each one individually.

Another corner of the ECG market concerns itself with the ECG electrodes used for connecting the machine directly to the patient in such a way as to prevent the possibility of electric shock. This demonstrates that there is also a large market for accessories for what would appear to be a self enclosed system.

A number of steps where taken to insure an efficient design. The system was constructed so as to minimise the number of parts required for construction. For instance the decision to use a 074 opamp instead of an 741 meant that only one chip instead of two was required, this was due to the fact that the 074 chip contains 4 opamps where as the 741 only contains 2 opamps and both the chips are the same price and the same size. Also standard components were used which were known to be reliable and also cost effective to obtain. Some chips used were multi-functional and wastage of components was limited, a single NOT chip was used for the entire circuit. The construction of the board was also effective as all the chips that were wire wrapped where placed in chip holders meaning they could easily be removed should any fault or malfunction occur. The system was build in sections and also, with the addition of a free running header, included its own self testing facility which is the sign of a good design. Over all the design was of an efficient construction, standard power inputs were used ( +5v and -5v) and even the inputs of the opamps were reduced to the standard 5v, therefore removing the need for additional circuitry to provide the '+7.5','-7.5' which was originally planned.

Further additions to the circuitry could be the introduction of several inputs and outputs to make the system more efficient for the end user. Also an all enclosed system with its own display unit and its own power supply would make it appear more of a 'product' that would appeal to the consumer market. Overall with the market already overwhelmed with the amount of ECG products available and every possibly technical utility a Doctor could want, it would be not be viable to develop this system to any further stage than it already is as the possibilities of getting a return on invest are minimal at best.

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